1. Field of the Invention
This invention relates to the field of retentative logic devices, such as latches and flip-flops. More particularly it relates to the field of high speed latches and flip-flops which have true or simultaneously occurring complementary outputs and which utilize minimum substrate area.
2. Description of the Prior Art
Several prior art circuits utilize simple inverters and transmission gates in the design of latches and flip-flops. One such device is the master/slave Toggle flip-flop shown in FIG. 1. This device is composed of identical master and slave latches which are connected together in a manner to produce the toggle action. The master latch comprises a transmission gate 22 coupled serially to inverters 24 and 26. The slave latch comprises a transmission gate 32 coupled serially to inverters 34 and 36. The output of inverter 26 is connected through a transmission gate 40 to the input of inverter 24. The output of inverter 36 is connected through a transmission gate 42 to the input of inverter 34. Clock and clock lines 52 and 54 are each coupled to the several transmission gates. Output lines Q and Q are designated 56 and 58 respectively.
In this general type of configuration, the Q output signal is obtained by additionally passing the Q output signal through an inverter gate. This introduces one gate delay of time between the establishment of the Q and Q output signals. A major disadvantage of circuits such as that of FIG. 1 is that the inverting output signal Q and the non-inverting output signal Q do not change states simultaneously. Complementary logic signals which change states at substantially the same time are referred to as true complementary signals. The outputs can be forced to become truly complementary by introducing an additional propagation delay at the Q output. This, however, requires more substrate area and reduces the speed of the latch.
FIG. 2, shows a timing diagram for the prior art Toggle flip-flop of FIG. 1. The period between times TA and TB is an initialization stage. During this time period the clock signal at line 52 is at a logical low and at line 54 is at a logical high; a logical low level is present at node 62 and line 56; and logical high levels are present at nodes 60, 64, 66 and line 58.
FIG. 2A shows the clock input signal present at line 52. FIG. 2B shows the clock input signal present at node 54. FIG. 2C shows the signal present at node 60. FIG. 2D shows the signal present at node 62. FIG. 2E shows the signal present at node 64. FIG. 2F shows the signal present at node 66. FIG. 2G shows the Q output signal present at line 56. FIG. 2H shows the Q output signal present at line 58.
At time TB the clock signals at lines 52 and 54 make the transition to logic high and logic low respectively. This disables transmission gates 22 and 42 while enabling transmission gates 40 and 32. This action latches the previous state into the master latch and allows the master to drive the slave into a new state.
The delay T1 in the signal at node 66 represents the time required for inverter 24 to discharge the stray capacitance associated with node 66 through transmission gate 32. The delay T2 on line 56 represents the gate delay associated with inverter 34. The delay T3 on the signal at line 58 represents the gate delay of inverter 36. The total delay required to establish a new state in the slave equals T1+T2+T3. It should be noted that the Q output signal at line 58 switched one full gate delay after the Q output signal at line 56.
At time TC another clock transition takes place. This transition disables transmission gates 40 and 32 while enabling transmission gates 22 and 42. This in turn latches the new state of the slave and allows the slave to drive a new state into the master. The T1 delay on the signal at node 60 represents the time required for inverter 36 to discharge the stray capacitance associated with node 60 through transmission gate 22. The delay T2 on the signal at node 62 shown in FIG. 2D represents the gate delay of inverter 24 and the delay T3 on the signal at node 64 represents the gate delay of inverter 26. The delay required to set a new state into the master equals T1+T2+T3 for a total of 3 propagation delays.
The fastest toggle rate of the conventional Toggle flip-flop is the time required to set a new state in the master plus the time required to set a new state in the slave. That is, the fastest toggle frequency is 1/(2 T1+T2+T3).
The previous and subsequent analysis of both the high speed flip-flop of the present invention and the conventional flip-flop is made using equal sized P-channel gate areas and equal size N-channel gate areas. In addition to this, the gate area ratio of the P-and N-channel devices assume equal drive for sink and source capabilities. Both flip-flops are also unloaded. Additional capacitance on the output nodes of each flip-flop will reduce the speed of each flip-flop by an equal amount.
A severe limitation of the design of the device of FIG. 1 is that three (3) propagation delays are encountered between a master (or slave) output and a master (or slave) input. This results in relatively slow operation of the flip-flop. In order to make the device of FIG. 1 operate at high speeds necessitated by high frequencies, very large area devices are required when the flip-flop is implemented in CMOS (Complementary Metal Oxide Semiconductor). By contrast, the present invention contains more active devices than many prior art flip-flops, but a significant reduction in propagation delays enables the invention to operate at much higher frequencies and utilize much smaller transistors such that the overall substrate area required for high frequency operation is smaller than that of the prior art.